A SPI bus has four logical signals:
- SCLK: Serial Clock (output from master; aka SCK; CLK);
- MOSI; SIMO: Master Output, Slave Input (output from master; aka SDI; DI, DIN, SI);
- MISO; SOMI: Master Input, Slave Output (output from slave; aka SDO; DO, DOUT, SO: Serial Data Out; Data Out, Serial Out);
- SS: Slave Select (active low, output from master; aka nCS, CS, CSB, CSN, nSS, STE: Chip Select, Slave Transmit Enable).
In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide names these two options as CPOL (aka CKP - Clock Polarity) and CPHA (aka CKE - Data Clock Edge) respectively, and most vendors have adopted that convention.
References:
SPI Introduction
SPIGen
SPI Block Guide V03.06
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